智原科技1993年成立於台灣新竹科學園區,提供ASIC服務(特殊應用積體電路)與矽智財IP授權服務,為亞洲第一家ASIC廠商,陸續在美國、日本、中國、印度與越南設立研發、行銷據點,提供全球客戶即時的服務。智原科技在台灣證券交易所上市,股票代碼為3035。
智原科技公司專做介紹影片:
https://www.linkedin.com/posts/faraday_corporate-video-faraday-activity-6884779550455296000–L5c
104職缺連結:
3.SOC Physical Design Engineer
職缺名稱 | 工作內容 | 工作待遇 | 工作地點 | 管理責任 | 上班時段 | 學歷要求 | 學歷要求 | 工作經歷 | 其他條件 |
ASIC Consultant Engineer | 1. Responsible for the main technical contact window and consultant of chip implementation from RTL-in/netlist-in to tape out for ASIC customers 2. Responsible for ASIC project management and coordination among internal supporting groups 3. Responsible for DFT implementation, including MBIST, Scan insertion, IO level testing, JTAG and ATPG generation 4. Responsible for ASIC constraint validation, including floorplan, timing, clock, package, power, and so on. |
面議 | 花蓮市 | 不需負擔管理責任 | 日班/週休二日 | 大學、碩士 | 資訊工程相關電機電子工程相關 | 不拘 | 1.Experienced in advanced node process is a plus 2.Experienced in chip design flow and chip implementation flow 3. Familiar with EDA tools including PrimeTime, Debussy, Verilog-XL, Design Compiler, and formal verification tools 4. Familiar with DFT related flow and utilities is a plus 5. Interested in communicating with people 6. Training in Hsinchu HQ, depending on training result to relocate in Hualien |
ASIC Consultant Manager | 1. Responsible for the main technical contact window and consultant of chip implementation from RTL-in/netlist-in to tape out for ASIC customers 2. Responsible for ASIC project management and coordination among internal supporting groups 3. Responsible for DFT implementation, including MBIST, Scan insertion, IO level testing, JTAG and ATPG generation 4. Responsible for ASIC constraint validation, including floorplan, timing, clock, package, power, and so on. |
面議 | 花蓮市 | 需負擔管理責任,管理人數待定 | 日班/週休二日 | 大學、碩士 | 資訊工程相關電機電子工程相關 | 3年以上 | 1.Experienced in advanced node process is a plus 2.Experienced in chip design flow and chip implementation flow 3. Familiar with EDA tools including PrimeTime, Debussy, Verilog-XL, Design Compiler, and formal verification tools 4. Familiar with DFT related flow and utilities is a plus 5. Interested in communicating with people 6.Experienced in management is a plus 7. Training in Hsinchu HQ at least 6 months, depending on training result to relocate in Hualien |
SOC Physical Design Engineer | 1. Responsible for ASIC physical implementation by using automatic place and route tools. The P&R processes including floorplanning, power plan synthesis and analysis, physical timing optimization, clock tree synthesis, routing, and post-routing optimizations. 2. Responsible for physical verification including DRC, LVS and ESD checking. |
面議 | 花蓮市 | 不需負擔管理責任 | 日班/週休二日 | 大學、碩士 | 電子電機相關資訊工程相關 | 不拘 | 1.Experienced in advanced node process is a plus 2. BS or MS degree in EE or CS related 3. Experienced in Cadence Innovus flow or Synopsys ICC2 flow 4. Experienced in hierarchical implementation, timing closure, IR drop analysis, crosstalk analysis is a plus 5. Experienced in physical verification and layout editing is a plus 6.Training in Hsinchu HQ at least 6 months, depending on training result to relocate in Hualien |
SOC Physical Design Manager | 1. Responsible for ASIC physical implementation by using automatic place and route tools. The P&R processes including floorplanning, power plan synthesis and analysis, physical timing optimization, clock tree synthesis, routing, and post-routing optimizations. 2. Responsible for physical verification including DRC, LVS and ESD checking. |
面議 | 花蓮市 | 需負擔管理責任,管理人數待定 | 日班/週休二日 | 大學、碩士 | 電子電機相關資訊工程相關 | 3年以上 | 1.Experienced in advanced node process is a plus 2. BS or MS degree in EE or CS related 3. Experienced in Cadence Innovus flow or Synopsys ICC2 flow 4. Experienced in hierarchical implementation, timing closure, IR drop analysis, crosstalk analysis is a plus 5. Experienced in physical verification and layout editing is a plus 6. Experienced in management is a plus 7. Training in Hsinchu HQ at least 6 months, depending on training result to relocate in Hualien |